As the microelectronics industry has advanced, integrated circuit (IC) designs have experienced dramatic increases in both density and speed. The reason for these increases is largely due to the decreasing feature sizes with which IC devices are manufactured. "Feature size" refers to the minimum gate length of a CMOS transistor.
Single Event Upset Problem
The inventors work in an area of developing IC devices suitable for space-bound technologies, such as satellites, interplanetary probes, or manned space shuttles. Space application presents a whole host of design issues for semiconductor technologies. IC chips are subjected to hostile environments in space that result in total ionizing dose effects primarily due to interactions with trapped electrons and protons as well as single event effects (SEE) caused by interactions with cosmic rays (high energy heavy ions), high energy protons, and high energy neutrons. Of these effects, single event upsets (SEUs) represent the radiation-induced hazard most difficult to avoid in spaceborne microelectronics systems.
Consider the effects concerning energy loss, charge collection, and upset due to a cosmic ray striking a junction in an IC device. When an energetic ion passes through any material, it looses energy through interactions with the material. The energy loss is primarily due to interactions of the ion with the bound electrons in the material, causing an ionization of the material and the formation of a dense track of electron-hole pairs. The rate at which the ion looses energy is historically termed the stopping power (dE/dx). The incremental energy dE is usually measured in units of MeV while the material thickness is usually measured as a mass thickness in units of mg/cm.sup.2. The term LET (linear energy transfer) is often used to mean stopping power.
In silicon, 3.6 eV of energy is needed to create a single electron-hole pair. From the density of silicon (2.42 gm/cm.sup.3), a one micron thickness converts to a mass thickness of 0.242 mg/cm.sup.2. Also one electron charge equals 1.60.times.10.sup.-7 pico-Coulomb (pC). Therefore, in silicon, the amount of electron-hole pairs dQ along a track of length L for an ionizing particle having a stopping power LET is given by: EQU dQ(pC)=0.011.times.L(microns).times.LET(Mev-cm.sup.2 /mg)
Thus, an ion with an LET of 100 Mev-cm.sup.2 /mg leaves approximately 1 pC of electron-hole pairs along each micron of its track.
In bulk silicon, the electron-hole pairs are of no consequence since they will eventually recombine. In the presence of electric fields, however, the electron-hole pairs will be quickly separated as they drift in opposite directions in the field and will be quickly collected by whatever voltage sources are responsible for the field. In bulk CMOS ICs, such electric fields are present across every pn junction in the device. Each and every circuit signal node in the IC device is typically isolated from Vdd by one or more such junctions (PMOS transistor drains) and isolated from ground (Vss) by one or more such junctions (NMOS transistor drains).
FIG. 1 illustrates the effect of an ion passing through an NMOS drain junction on an IC chip. FIG. 1 shows a cross-section of a drain junction 20 having an n+ NMOS drain 22 diffused into a p- epitaxial (epi) layer 24 on a p+ substrate 26. The junction 20 isolates a circuit node at positive voltage (+V) relative to the substrate voltage (Vss). The ion passing through the junction 20 produces a dense track 30 of electron-hole pairs, which are represented by the "+" symbol for electrons and the "-" symbol for holes. The electron-hole pairs behave much like a conductive plasma, which perturbs the potential contours forming a funnel region 32.
A prompt component of current is observed at the circuit signal node as the electric field in the junction and funnel regions separate the electron and hole free carriers. For the geometry of FIG. 1, electrons are collected by the circuit node and holes are collected by the substrate node resulting in a negative current pulse on the NMOS diffusion node which tends to discharge the signal voltage. This prompt current pulse is short-lived, lasting on the order of only 100 to 200 picoseconds.
A delayed current component is produced by diffusion of the electrons and holes from regions where the electric field is zero. These charges may, if they do not recombine, eventually reach a field region where they are collected. This delayed component may last as long as several hundred nanoseconds.
Little charge is collected from the p+ substrate region since the recombination rate is high due to the high doping concentration. If the signal voltage on an NMOS drain is zero, the electric fields will be essentially zero and no appreciable charge collection will occur.
Similar processes occur in the vicinity of PMOS drain diffusions formed in n-wells biased to Vdd. In this case, electric fields are present and charge is collected by the PMOS drain if the signal voltage is at zero volts. The collection depth for this case is less (approximately one-half the well depth) since the well-substrate junction is always reverse biased and will also collect charge.
High energy protons and neutrons are also known to produce similar effects indirectly through nuclear reactions within the silicon. In these cases, a heavy ion recoil reaction byproduct passes through a junction and produces a similar charge collection current pulse. In space, high energy protons primarily originate from the trapped protons in radiation belts and from solar flares. For high-altitude aircraft, both high energy neutrons and protons are encountered as reaction byproducts found in cosmic ray showers formed when an energetic heavy ion from space undergoes a nuclear reaction in the atmosphere.
The prompt current component described above has been responsible for SEUs observed in spaceborne circuits over the last 10-15 years. Most notably, the SEUs are detected in static latches and SRAMs (static random access memories). The effect that the near-instantaneous current has on the circuit depends on the response of the circuit to the charge collected on the signal node. Basically, the capacitance of the signal node determines (to first order) how large a voltage swing dV will result from the collection of a charge dQ according to dV=dQ/C. (This is exact only in the approximation that the circuit is too slow to dissipate the charge in several hundreds of picoseconds.) High drive transistors mitigate this effect since they dissipate the collected charge more quickly. Also, and most importantly for latches and SRAMs, positive gain feedback loops cause a data bit flip once the collected charge reaches a critical value (Qcrit) sufficient to drive a node voltage past the switching voltage. More detailed discussions of these effects, and SRAM circuit response in particular, can be found in Dodd, P. E. and F. W. Sexton, "Critical Charge Concepts for CMOS SRAMs", IEEE Transactions on Nuclear Science, Vol. 42, No. 6, December 1995, pp. 1764-1771.
Feature Size Reduction Heightens SEU Problem
SEUs become more problematic as feature size decreases. Features sizes in non-radiation hardened commercial fabrications have shrunk below 1.0 micron (several years ago) to 0.18 microns (currently) and continue to shrink to a projected 0.05 microns (by the year 2012).
To achieve this reduction, a number of scaling models have been used in the industry, including lateral scaling where only the gate length is scaled, constant voltage scaling where the supply voltage Vdd is kept constant, and constant field scaling where Vdd is decreased as the gate oxide thickness is decreased to maintain a constant electric field in transistors. The constant field scaling model has proven to be the most practical since it avoids several deleterious effects of high fields (gate oxide breakdown and hot electrons).
For constant field scaling, as all physical device dimensions (such as gate length L, gate width W, and gate oxide thickness T.sub.ox) are reduced, the supply voltage Vdd and the threshold voltage Vth are also reduced proportionately. This results in proportionately lower drain current (I), proportionately lower load capacitance (C), and proportionately lower circuit gate delay (C*Vdd/I). The lower transistor current for constant field scaling also means that metallization current densities (responsible for electromigration) increase less rapidly than for constant voltage scaling for which transistor current remains constant. Also, for low power systems, constant field scaling (in which Vdd scales proportionately) is the only viable alternative since it results in substantially lower (by the square of the scaling) power dissipation.
Spaceborne microelectronics typically lag behind their commercial counterparts by one or two generations because of the more complicated fabrication steps needed to achieve the total-dose hardening requirements of space. Radiation-hardened ICs are presently being fabricated in 0.8 micron to 0.7 micron feature sizes. SEU in static latches and SRAMs became an important issue once feature sizes dropped below 10 microns and the critical charge for upsetting a circuit dropped below 1 pC (roughly corresponding to a particle LET of 50 MeV-cm.sup.2 /mg and a collection depth of two microns). It has really been the internal feedback loops within the latches that made SEUs important over the last decade for these types of circuits.
Static latch SEU vulnerability has been calculated and measured as a function of technology feature size to establish the relationship between the critical charge needed to upset the circuit and the technology feature size. All results indicate that the critical charge needed to upset a latch decreases as the square of the feature size. If this relation holds as electronics feature sizes decrease from 0.8 micron (present day spaceborne) to 0.18 micron (present day commercial), the critical charge will decrease by nearly a factor of 20.
Experimentally observed LETs for 0.8 micron standard cell latch designs have been as low as 5 MeV-cm.sup.2 /mg and as high as 20 MeV-cm.sup.2 /mg. Even with thinner epitaxial layers, 0.18 micron designs could have SEU threshold LETs no higher than 1 MeV-cm.sup.2 /mg. While the area cross section for a heavy ion hit will be a factor of 20 lower, the integral fluency of cosmic rays above 1 MeV-cm.sup.2 /mg is 1000 times larger than the fluency above 20 MeV-cm.sup.2 /mg for a geosynchronous orbit. This implies an SEU error rate (per bit) increase of a factor of 50. Since 0.18 micron designs will likely have 20 times the number of latches on a given die size as 0.8 micron designs, the total IC error rate will be 1000 times larger.
Past Solutions to SEU Problem
Previous solutions to alleviate the SEU problem have focused on SRAM and latch designs. Some of the most interesting work has focused on latches for use in ASIC (application specific integrated circuit) designs, although the results can conceivably be applied to SRAM designs.
One such latch is described in U.S. Pat. No. 5,311,070 to Dooley, J. G., entitled "SEU-Immune Latch for Gate Array, Standard Cell, and other ASIC Applications". This latch design uses a cross-isolation method to ensure that the state of the latch cannot be altered by a heavy ion strike on any single critical node.
Another design is presented in Calin, T., M. Nicolaidis, and R. Velazco, "Upset Hardened Memory Design for Submicron CMOS Technology", IEEE Transactions on Nuclear Science, Vol. 43, No. 6, December 1996, pp. 2874-2878. This design, termed the DICE (dual interlocked storage cell) latch, also cannot be upset with a single node strike.
Each of these latches can, however, be upset if a single cosmic ray traveling through the IC at a shallow angle nearly parallel the surface of the die simultaneously strikes two sensitive junctions. The geometrical cross section for this happening, while small, may still be significant for some spaceborne applications.
Single Event Transient Problem for Sequential Circuits
Apart from inducing SEUs at the gate and substrate level, cosmic rays can also induce single event transients (SETs) in combinatorial logic, in global clock lines, and in global control lines at the circuit level. The SETs have only minor effects in present 0.8 to 0.7 micron technologies since the speed of these circuits is insufficient to propagate the 100 to 200 ps SET any appreciable distance through the circuit. However, as smaller feature size (and thus faster) technologies find their way into spaceborne systems, these transients will be indistinguishable from normal circuit signals.
FIG. 2 shows a log graph plotting the critical transient pulse width needed to propagate an SET without attenuation through an infinitely long chain of inverters as a function of technology feature size. At pulse widths smaller that the critical pulse width, the inherent inertial delay of the gate causes the single event transient to be attenuated. The SET dies out after passing a few gates. At pulse widths equal to or larger than the critical pulse width, the single event transient propagates through the gate just as though it is a normal circuit signal. As a general rule of thumb, SETs of pulse width greater than the critical width propagate through any number of gates without attenuation; SETs of pulse width less than half the critical width terminate in the first gate; and SETs of intermediate pulse width propagate through a varying number of stages.
The curve in FIG. 2 is the result of SPICE simulations performed for various technology feature sizes (shown by the dots on the curve) between 1.2 microns (1200 nm) and 0.13 microns (130 nm). A generic set of SPICE model parameters was developed using known model parameters for technology sizes between 1.2 microns and 0.7 microns, inclusive. The constant field scaling rules were applied to the generic model and to the transistor sizes to predict model parameters at the smaller feature sizes. The scaled values of various critical parameters (Vdd, Vth, and Tox) were consistent throughout with projections published in the National Technology Roadmap for Semiconductors. The solid curve connects the simulation points while the dashed curve extrapolates the points to 0.05 micron (50 nm), the projected feature size of commercial technologies in the year 2012.
As discussed earlier, cosmic ray-induced transients have pulse widths of 100 to 200 picoseconds. FIG. 2 confirms that by the next one or two generations of spaceborne microelectronics systems, which employ ICs with feature sizes below 0.35 microns, SETs will no longer be attenuated within the gates of a circuit, but instead will propagate as normal circuit signals. This will have serious, if not grave, implications for sequential circuits.
FIG. 3 illustrates a conventional circuit topology for a sequential circuit 40. The circuit 40 has a first latch 42, combinatorial logic block 44, and a second latch 46. In this illustration, the latches 42 and 46 are implemented as D flip-flops. The data from the first latch 42 is typically released to the combinatorial logic 44 on a falling clock edge, at which time logic operations are performed. The output of the combinatorial logic 44 reaches the second latch 46 sometime before the next falling clock edge. At the falling clock edge, the second latch 46 stores whatever data happens to be present at its input and meeting the setup and hold times.
If a heavy ion strike occurs within the combinatorial logic block 44 and the logic is fast enough to propagate the induced transient, the SET eventually appears at the input of the second latch 46 where it may be interpreted as a valid signal. Whether or not the SET gets stored as real data depends on the temporal relationship between its arrival time and the falling edge of the clock.
FIG. 4 shows a timing diagram to illustrate the temporal relationship for the case that the true data is low and a positive SET appears erroneously at the input to the second latch 46. FIG. 4 shows a clock signal 50 and four different SET signals 52-58 illustrating four cases at which an SET can arrive in relation to the falling edge of the clock signal 50.
The transient will be incorrectly interpreted as valid data and subsequently stored in the latch if it is high during the time period extending from a setup time before the clock edge and to a hold time after the clock edge. The latch is presumed to be fast enough so that the setup time plus hold time is less than the width of the SET. In FIG. 4, the first SET signal 52 occurs before this interval, and hence is not latched in the second latch 46. The fourth SET signal 58 occurs after this interval, and again does not result in a latched state. However, the second and third SET signals 54 and 56 represent the earliest and latest, respectively, arrival times for a latching condition in which the SET signal is erroneously stored in latch 46.
FIG. 5 shows another timing diagram that illustrates the temporal relationship for another type of SET that can cause invalid data to be stored in the latch. In this case, the SET occurs on the clock line itself. FIG. 5 shows a data signal 60, a normal clock signal 62, and three different clock signals 64-68 that are corrupted by an SET (represented by the dashed line in each case).
The true data 60 satisfies the latch setup and hold times relative to the falling clock edge in order for it to be correctly stored under normal circuit operation as represented by clock signal 62. Clock signal 64 contains a negative SET on the clock line, which causes the falling edge of the clock signal to fall prematurely. As a result, a low value for the data signal 60 is incorrectly stored.
Clock signal 66 shows a positive SET intermediate of the asserted high data signal. The SET in clock signal 66 does not cause any problems since it comes and goes after the high data has been stored and while the data remains high. Clock signal 68 contains a positive SET during the falling edge of the data signal 60. The SET in clock signal 68 causes the latch to store erroneously a low in place of the previously stored high. It is noted that the transient need not be coincident with the falling edge of the data signal to cause a problem. The latch will be corrupted for any clock line transient whose falling edge is later than the data falling edge.
Relation of Clock Frequency to SEUs and SETs
Various error rates in sequential circuits (i.e., latch SEU and combinatorial logic SET) depend on the clock frequency. Upsets can occur in latches only when the clock is low and the latch is in a hold state. Since the clock is always low 50% of the time, latch SEU rates do not depend on the clock frequency. However, SETs produced in the combinatorial logic will be stored if they reach the latch input coincident with clock edges, the number of which depend linearly on the frequency. Accordingly, the SEU rate for latches is independent of clock frequency while the combinatorial logic SET error rate is directly proportional to clock frequency. These error rate relations have been demonstrated experimentally using pulsed laser illumination of test circuits while measuring the various error rates as a function of clock frequency in Buchner, S., M. Baze, D. Brown, D. McMorrow, and J. Melinger, "Comparison of Error Rates in Combinatorial and Sequential Logic", IEEE Transactions on Nuclear Science, Vol. 44, No. 6, December 1997, pp. 2209-2216.
These error rate relations actually compound the SET problem as IC technology feature sizes continue to shrink. Smaller feature sizes result in smaller gate delays that permit circuits to be operated at higher clock frequencies. Not only does each combinatorial gate in a circuit contribute transient errors (because transients are no longer attenuated), but the probability of storing any given error also increases (because of the higher clock frequencies).
To date, efforts in the area of SETs have been limited to characterizing the mechanisms, simulating the propagation process, and developing analytical tools to estimate error rates in future designs. Despite these efforts, there remains a substantial need for techniques to eliminate errors introduced by single event upsets and single event transients.
The inventors have developed circuit techniques to solve the SET problem as well as the conventional static latch SEU problem.